The present invention relates generally to delay lines and more particularly to variable delay lines.
In handling electrical signals it is occasionally useful to introduce delays. Such delays are particularly useful in sonar applications.
Variable delay lines are known having taps which divide the line into a plurality of delay segments whose delay values are fixed. A sample of a waveform applied to the input of the line will be received at any tap after a delay equal to the sum of the delays introduced by the intervening delay segments. Examples of such delay lines include shift registers wherein outputs may also be tapped off at intermediate stages.
Variable delay lines are also known having a line length which can be varied. A sample of a waveform applied to the input of the line will be received at the output after a delay equal to the delay introduced by the intervening length of line. An example of such a line is the variable-length shift-register integrated circuit, such as the Motorola MC 14557, wherein the desired register length (number of bits) and therefore time delay (for a given clock rate) is programmed by supplying to the register a digital code word representing the delay.
A need exists for a variable delay line having multiple taps as well as intervening segments whose delay values can be varied under control of an external circuit. Such a delay line might be constructed from the above-mentioned variable delay lines but would require extremely complicated switching or encoding circuitry.